Verilog RTL has a synthesisable subset that can be turned into circuits.
Synthesisable Verilog uses one of the following forms and these may be mixed within one module:
The 'Pure RTL' forms have one list of assignments for each clock domain. The order of statements is unimportant in a list. A list without a clock domain is for combinational logic (continuous assignments).
|4: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.|