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Structural Verilog

Level 1/3: Structural Verilog: a structural netlist with hierarchy.

    module subcircuit(input clk, input rst, output q2);
       wire q1, q3, a;
       DFFR Ff_1(clk, rst, a, q1, qb1),
            Ff_2(clk, rst, q1, q2, qb2),
            Ff_3(clk, rst, q2, q3, qb3);
      NOR2 Nor2_1(a, q2, q3);

Just a netlist.

There are no assignment statements that transfer data between registers in structural RTL (but it's still a form or RTL).

6: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.   TAPE MISSING ICON