»Definitions (some authors vary slightly):
(Where the address to a register file has not yet arrived we have a data hazard on the address itself, but this could be regarded as a control hazard for the register file operation itself (read or write).)
We have a structural hazard when an operation cannot proceed because a resource is already in use.
Resources that might present structural hazards are:
A fully-pipelined component can start a new operation on every clock cycle. It will have fixed latency (pipeline delay). Non-fully pipelined components generally have handshake wires that start it and inform the client logic when it is ready and often have variable latency.
Synchronous RAMs, and most complex ALUs excluding divide, are generally fully pipelined and fixed-latency.
|35: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.|