The RTL languages (Verilog and VDHL) are used both for simulation and synthesis. Any RTL can be simulated but only a subset is standardised as `synthesisable' (although synthesis tools can generally handle a slightly larger synthesisable subset).
Simulation: uses event-driven simulation (EDS). When using zero-delay models, we use the compute/commit paradigm where the EDS kernel is augmented to support delta cycles.
Synthesis: involves converting to a parallel form with one right-hand-side expression per variable. Then converting each expression to a logic tree, preferably taking into account sub-expression sharing and user speed/power/area requirements.
Simulation uses a top-level test bench module with no inputs.
Synthesis runs are made using points lower in the hierarchy as roots. We should certainly leave out the test-bench wrapper when synthesising and we typically want to synthesise each major component separately.
|13: (C) 2012-17, DJ Greaves, University of Cambridge, Computer Laboratory.|