Advanced Topics in Computer Architecture

Reading List

Note: All Week 1 papers are not for assessment. You should not submit an essay on the topic of these papers.

Week 1: Trends in Computer Architecture

• Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures Agarwal, Hrishikesh, Keckler and Burger, ISCA, June 2000.
  [ IEEE Xplore ]
• Dark Silicon and the End of Multicore Scaling Esmaeilzadeh et al, IEEE Micro, 32:2, May-June 2012.
  [ IEEE Xplore ]
• The Accelerator Wall: Limits to Chip Specialization Fuchs and Wentzlaff, HPCA 2019.
  [ IEEE Xplore ]

Other optional material for week 1

• A New Golden Age for Computer Architecture Hennessy and Patterson, Communications of the ACM, Feb. 2019, 62(2), pp. 48-60 (Turing Lecture)
• Sophie Wilson, "The Future of Microprocessors", 2020 Wheeler Lecture, University of Cambridge, May 2020

Week 2: State-of-the-art Processor Design

• BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28nm CMOS Celio, Chiu, Asanovic, Nikolic and Patterson. Hot Chips 30, 2019.
  [IEEE Xplore ]
• Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake Doweck et al, IEEE Micro, vol. 37, 2017
  [IEEE Xplore ]
• The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips Davidson et al. IEEE Micro, 38(2), March-April, 2019
  [IEEE Xplore ]

Other optional material for week 2

• Samsung M3 Processor Rupley, Burgess, Grayson, Zuraski, IEEE Micro, 39(2), March-April, 2019
  [IEEE Xplore ]

Week 3: Memory system design

• Berti: an Accurate Local-Delta Data Prefetcher Navarro-Torres, Panda, Alastruey-Benedé, Ibáñez,Viñals-Yúfera and Ros, MICRO 2022
  [IEEE Xplore]
• Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction Bera, Kanellopoulos, Balachandran, Novo, Olgun, Sadrosadat and Mutlu, MICRO 2022
  [IEEE Xplore]
• Temporal Prefetching Without the Off-Chip Metadata Wu, Nathella, Pusdesris, Sunwoo, Jain and Lin, MICRO 2019
  [ACM Digital Library]

Other optional material for week 3

• RnR: A Software-Assisted Record-and-Replay Hardware Prefetcher Zhang, Zeng, Shalf and Guo, MICRO 2020
  [IEEE Xplore]
• Prodigy: Improving the Memory Latency of Data-Indirect Irregular Workloads Using Hardware-Software Co-Design Talati, May, Behroozi, Yang, Kaszyk, Vasiladiotis, Verma, Li, Nguyen, Sun, Morton, Ahmadi, Austin, O'Boyle, Mahlke, Mudge and Dreslinski, HPCA 2021
  [IEEE Xplore]

Week 4: Hardware reliability

• Sampling + DMR: Practical and Low-overhead Permanent Fault Detection Nomura, Sinclair, Ho, Govindaraju, de Kruijf and Sankaralingam, ISCA 2011
  [ACM Digital Library]
• Asymmetric Resilience: Exploiting Task-level Idempotency for Transient Error Recovery in Accelerator-based Systems Leng, Buyuktosunoglu, Bertran, Bose, Chen, Guo and Reddi, HPCA 2020
  [IEEE Xplore]
• Demystifying the System Vulnerability Stack: Transient Fault Effects Across the Layers Papadimitriou and Gizopoulos, ISCA 2021
  [IEEE Xplore]

Other optional material for week 4

• Detecting silent data corruptions in the wild Dixit, Boyle, Vunnam, Pendharkar, Beadon and Sankar, 2022
  [arXiv]
• BRAVO: Balanced Reliability-Aware Voltage Optimization Swaminathan, Chandramoorthy, Cher, Bertran, Buyuktosunoglu and Bose, HPCA 2017
  [IEEE Xplore]

Week 5: Specification, verification and test

• Who Guards the Guards? Formal validation of the Arm v8-m architecture specification, OOPSLA 2017
  [ACM Digital Library]
• Genesys-Pro: Innovations in Test Program Generation for Functional Processor Verification, IBM Research, IEEE Design and Test 2004
  [IEEExplore]
• End-to-end verification of processors with ISA-Formal, ARM Ltd, CAV 2016
  [Open Access]

Other optional material for week 5

• Theme 1: Formal specification of ISAs:
• ISA Semantics for ARMv8-A, RISC-V, and CHERI-MIPS, POPL 2019
  [Open Access]
• Sail RISC-V docs:
  [GitHub]
• Theme 2: Instruction test generation:
• Randomised testing of a microprocessor model using SMT-solver state generation, 2015
  [Science Direct]
• RISC-V torture tests:
  [GitHub]

Week 6: Security 1: CHERI

• The Arm Morello Evaluation Platform—Validating CHERI-Based Security in a High-Performance System, IEEE Micro 2023. DOI: 10.1109/MM.2023.3264676
  [IEEExplore Library]
• Efficient Tagged Memory, ICCD 2017
  [Open access]
• CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety, MICRO 2019
  [Open access]

Other papers/reports

• Companion to CHERIvoke: Cornucopia: Temporal Safety for CHERI Heaps. In Proceedings of the 41st IEEE Symposium on Security and Privacy (Oakland 2020). San Jose, CA, USA, May 18-20, 2020
  [Open access]
• For reference: Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 9)
  [Technical Report]
• More microarchitecture (but rather complex): CHERI Concentrate: Practical Compressed Capabilities, IEEE Transactions on Computers 2019
  [Open access]

Week 7: Security 2: Speculative execution attacks

• Spectre attacks: Exploiting speculative execution, 2019 IEEE Symposium on Security and Privacy (SOSP)
  [MeltdownAttack.org]
• Speculative taint tracking: A comprehensive protection for speculatively accessed data, 2019 International Symposium on Microarchitecture (MICRO)
  [UIUC i-acoma group]
• Revizor: Testing black-box CPUs against speculation contracts, 2022 Conference on Architectural Support for Programming Languages and Operating Systems (SOSP)
  [Microsoft]

Week 8: Hardware accelerators and accelerators for machine learning

• Pushing the limits of accelerator efficiency while retaining programmability, Nowatzki, Gangadhar, Sankaralingam and Wright, HPCA 2016
• A Software-defined Tensor Streaming Multiprocessor for Large-scale Machine Learning, Abts et al., ISCA 2022
  [ACM Digital Library]
• Plasticine: A Reconfigurable Architecture For Parallel Patterns, Prabhakar et al., ISCA 2017

Other optional/background material for week 8

You may also be interested in the approaches taken by Tenstorrent, Graphcore and Esparanto.

The following papers are perhaps a little more hardware-centric but may also be of interest:

• Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks, Chen, Emer and Sze, ISCA 2016
• EIE: Efficient Inference Engine on Compressed Deep Neural Network, Han, Liu, Mao, Pu, Pedram, Horowitz and Dally, ISCA 2016
  [VIDEO] Song Han presenting work at ISCA
• NullHop: A Flexible Convolutional Neural Network Accelerator Based on Sparse Representations of Feature Maps
  Aimar et al., IEEE Trans. Neural Networks Learn. Syst. 30(3): 644-656 (2019)
• Efficient Processing of Deep Neural Networks: A Tutorial and Survey
  Sze, Chen, Yang, Emer, Proceedings of the IEEE, Vol. 105, No. 12, Dec. 2017

Lecture Slides

Seminar 1 - Trends in Computer Architecture

Seminar 2 - Superscalar processor Design (background)

Seminar 3 - Prefetching

Seminar 4 - Reliability

Seminar 5 - Testing

Seminar 6 - Security 1: CHERI

Seminar 7 - Security 2: Speculative Execution Attacks

Seminar 8 - HW accelerators and accelerators for machine learning