System on Chip Design and Modelling
Principal lecturer: Dr David Greaves
Taken by: MPhil ACS
Page will be updated as the course develops...
The taught part of this course takes place over 16 sesions of one hour
in SW02. The expected time allocation is that the Monday sessions
are nominally for lectures and the Wednesday sessions are practical
classes and group seminars, but there will be some weeks with Wednesday lectures.
The course has been arranged in four sections ... details still in flux while I determine the interests of the class.
SECTION 1: Low-level Modelling and Design Refactoring Problems
Section 1: Topics: Verilog RTL Design with examples. Basic RTL to gates
synthesis algorithm. Event-driven simulation cycle. Using signals,
variables and transactions for component inter-communication. SystemC
overview. Hazards, retiming, refactoring.
Slides 1.1: (RTL): Pack 1.1 Not all will be used.
Slides 1.2: (SystemC): Pack 1.2, Examples.
Section 1: Slides III (Design Flow): Pack 1.3 (short)
Section 1: Assessed work:
- Exercise: Tick 1 (due 26th Jan, 5 credits).
- Exercise: Tick 2 (due 2nd Feb, 5 credits).
SECTION 2: Design Partition and Hybrid Modelling.
Section 2: Topics: Bus and network structures. Architecture, design partition and
design database. ESL. IP-XACT.
Slides 2.0: (Soc Components) Please see next year's course.
Slides 2.1: (Technology and Design Partition) Pack 2.1
Slides 2.2: (ESL modelling/Architecture Exploration) Pack 2.2, ESL toy PRACTICALS.
Section 2: Reading List:
Section 2: Assessed work:
SECTION 3: Assertions, Higher-level Entry & Hands-on SOC Design
Section 3: Topics: Assertion-based testing. Temporal Logic, PSL, SVA.
Refinement, Synthesis from higher forms (SysML, OneSpin, Kiwi, Bluespec).
Slides 3.1: (Assertion-Based Design) Pack 3.1
Slides 3.2: (High-Level Synthesis) Pack 3.2
Section 3: Reading List:
NB: You can run your own PSL experiments using Modelsim. There is medium-sized
example in /usr/groups/ecad/mentor/modelsim/current/modeltech/examples/psl/verilog/modeling/dram_controller.
Section 3: Practical work: We will start with an ORP 1000
core that is already set up to run raw C code and also single-core
linux. This is available in Verilog RTL and as a cycle-accurate C
model and as a high-level ISS (for use with GDB). The C models can be
connected to a SystemC TLM bus/system model or to a cycle accurate
SystemC model. We will insert assertions and detect errors.
Section 3: Assessed work: To be added.
- Exercise: Tick 4 (due 23rd Feb, 5 credits).
- Exercise: Tick 5 (due 9th Mar, 5 credits).
Section 4: Topics: Real-world bus structures (AHB, AXI, BVCI), DRAM. Some examples (transactor synthesis, network synthesis, glue logic synthesis).
Slides 4.1: (Bus/NoC Structures) Pack 4.1
Slides 4.2: (SoC Topics (Scale, Power Control etc)) Pack 4.2
Slides 4.3: (Examples) Work In Progress!
Section 4: Practical work:
Design and testing a cache consistency system
and message passing or transactional memory for a multi-processor SoC
using TLM modelling in SystemC with the ORP 1K cores.
Section 4: Assessed work:
Primary Material: Tools
Tool setup for Computer Laboratory machines
is described here toolsetup/README.txt.
Primary Material: SystemC
Download and install SystemC on your own system (requires registration on systemc.org)
or use the provided distribution on the lab machines toolsetup/README.txt.
There are a number of on-line tutorials and examples, such as
Primary Material: RTL (Verilog/VHDL)
Much of the course uses SystemC, but some examples and exercises
are in RTL of VHDL/Verilog style.
A teach-yourself Verilog course is available from the Computer
Laboratory. Please register using firstname.lastname@example.org email address on
Another on-line tutorial for Verilog is here
See also the part IB undergraduate course notes for
ECAD and ARCH,
DJ Greaves Tutorial 1985.
PSL Property Specification Language
There are plenty of introductory and advanced on-line materials
for PSL, just google for them...
Here is the standardised manual:
Primary Material: ORP 1K Soft Core
The ORP open risc processor can be downloaded from OpenCores or from
The pre-built version, based on the Embecosm
downloads will be/is installed on the lab machines here: toolsetup/README.txt.
The coursework for this ACS module is assessed using six ticks and two
The ticks count in total for 30 percent and the mini-projects each count for 35 percent.
All coursework must be submitted both in corner-stapled hardcopy
and by zip file email by given deadlines. The email will contain
source code and a brief report in pdf format. This form
of cover sheet (available from receiption
or print your own) must be used on the top of all submissions and a
member of Student Admin staff must sign and date each hardcopy
submission as it is received.
A ten percent per day penalty will be
applied to late submissions. The penalty is applied until the earlier of
the hardcopy or email is received.
Six Proficiency Ticks
Proficiency Ticks account for 30 percent of the module credit in total.
Proficiency Ticks are marked on a scale of 1 to 5 and the full mark will be
awarded for simply meeting the tick requirements without extra credit
for presentation etc.. Ticks might sometimes be completed during the
practical classes. The ticks must be handed in to student admin in
hard-copy form and email by 4:00 pm on the Tuesday following the week where the
tick was set.
It is expected that most candidates will be awarded full credit for
their tickable work on first submission, but tickable work can be
resubmitted later in the term for re-assessment as desired.
Mini-project I: Structured Research Essay (30 Credits)
Structured Research Essay: System-Level Design Techniques.
The deadline for the Structured Research Essay is Monday March 15th
2009 (end of Lent full term).
Mini-project II / Essay II (40 Credits).
Mini-project II involves the design and testing of either a
message passing or transactional memory for a multi-processor SoC. An accompanying
report and research essay is needed.
DETAILS TO BE ADDED.
The deadline for Mini_project II / Essay II is the first day of Easter full term.
External moderation and assessment of the essays: Mr Peter Flake (Elda Technology Ltd).
Nominal time budget:
16 SW02 sessions,
4 post session supervisions,
20 private study,
10 proficiency ticks (excluding additional time during classes),
10 Mini-project I,
20 Mini-project II.
This is a total of 80 hours, mostly in the Lent Term but also (for mini-project II) during the easter break.
Easter Term Research Project: Suggestion
Subject: Power estimation of various memory communication and consistency models
while using high-level modelling.
In this project, a rough model of the power consumption for the various
IPC (inter-processor communication) configurations developed during the taught
and practical parts of the course will first be developed. Then the research will be to
explore how well the same results can be derived when using TLM modelling for
various parts of the system.
Taxonomy of power estimation methods:
1. Proper power estimates come from post-layout simulation,
2. Rough estimates come from post-synthesis, pre-layout simulation,
3. Very rough estimates come from pre-synthesis simulation of RTL,
4. Cycle-accurate SystemC should give the same as 3,
5. TLM models can be gradually moved away from cycle accuracy by
increasing the simulation quantum: how does this degrade the power estimate
accuracy? Do all plots of power versus cache/size, bus width and IPC
mechanisms preserve their qualitative shape, even if they are no longer
quantitatively accurate ?
Supervision: I am happy to serve as supervisor for this project. More than
one person may be intending to do it. I suggest they collaborate on infrastructure
and reading lists, but it is a condition of my supervision that the specific research questions
investigated and experimental goals do not overlap between candidates.
(C) 2010 David J Greaves.