SoC D/M Proficiency Tick 1: 5 marks.  RTL/SystemC.



Read: http://en.wikipedia.org/wiki/Sieve_of_Eratosthenes

Write a module using Verilog, VHDL or SystemC that computes the prime
numbers up to 10000 using the sieve method. The module should have
input nets (wires) for start and clock. The prime sieving should be
done using individual bits of an array of 8-bit words.  The primes
should be written to a second array and, when all generated, they
should be read out of your module using additional nets and a protocol
of your choice.

Write a testbench for module and run the module on the testbench. Make
sure the testbench prints out the answers.

Questions:
  q1. Does your module contain 'behavioural' code?  

  q2. Explain whether your module is 'synthesisable' ?  

  q3. Is there a structural hazard in your module ?

  q4. Explain in detail any changes needed in your module to
turn it into a 'Pure RTL' design.

Note: the terms above will be explained in the taught part of the course.

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Questions Arising:

>According to the description of exercise 1 “The prime sieving should
>be done using individual bits of an array of 8-bit words”.
>
>1) Since we need to find the prime numbers up to 10000, don’t we need
>16 bits to store each number?
>
>2) Does this sentence mean that we can find the prime numbers without
>using addition? I am referring to the “individual bits” part of
>the sentence.

 
The Sieve method uses an array of Booleans: this exercise asks you to
use each bit of an 8-bit array as a separate Boolean.  If the second
array is also one byte wide, then the answers will be stored over more
than one location. You may use the builtin '+' and '*' operators in the source
language, or you may instantiate components that do these functions (this sort
of decision will alter the written answers to the questions). The same
goes for the RAMs - you may instantiate a component or use the built-in arrays
and [ ] subscription operator.


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> Could you please explain a bit more about the protocol we should use to
> output the results? Perhaps you could suggest an example to study? Thank
> you.

http://www.cl.cam.ac.uk/teaching/0910/P35/obj/page31.html

The four-phase handshake is ideal. See above link.

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I have a question on question 4 of tick1:
> q4. Explain in detail any changes needed in your module to turn it 
> into a 'Pure RTL' design.
> 
>  
> 
> Does this actually mean that we should rewrite the program in pure RTL
> or just indicate which parts of it need to be changed in order to make
> it a 'Pure RTL' design? For example, if I am currently using
> behavioural code at some point, do I have to re-write this part of the
> code using only synchronous code? Or is it enough to say that this
> part of the program is not ‘Pure RTL’?

You dont need to rewrite it to make it work, just explain where it
would need changing and how 'eg introduce a holding register for blah,
or add a controller with a state that does foo'.

Note that 'synchronous' refers to how the clock signal is wired up and
this is a slightly different matter.


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>Hi, David, Could you please explain 'pure RTL' a little bit? A
>detailed example might be very helpful.  How can a non-pure RTL be
>converted into a pure one?

http://www.cl.cam.ac.uk/teaching/0910/P35/rtlslides/page12.html

I'm using the 'pure RTL' term denote a description that consists
entirely of a list of pairs, where each pair gives a register name and
the expression to be transferred into it.  This is much narrower than
what is supported by VHDL/Verilog.

Details for computer conversion are given in the later slides

http://www.cl.cam.ac.uk/teaching/0910/P35/rtlslides/page47.html

but I did not choose to cover that.  Instead I'm just expecting
you to explain the process by hand for this one example.

The example on this page was done by hand:

http://www.cl.cam.ac.uk/teaching/0910/P35/rtlslides/page11.html


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