Title: System-Level Design Techniques (30 Credits).


The deadline for Research Essay I is Monday March 15th 2009 (end of Lent full term). 

Research Essay I must be written to the structure given below and it
includes Mini-Project I. It is not necessary to generate separate,
working code for this exercise: instead, detailed code fragments and
sketches should be included in the essay itself.


The essay is expected to be somewhere above 2000 words and no longer
that 5500 words, excluding headings, citations, figures and footnotes
etc..




P1. Accelerating High-Level SysML and SystemC SoC Designs, By Waseem Raslan,

P2. Industrial IP Integration Flows based on IP-XACT™ Standards, by Wido Kruijtzer

P3. Straightforward IP Integration with IP-XACT RTL-TLM Switching, Marcin Zysś


The research essay should be based in the general area of the above three
papers, as discussed in our seminar, but of course, any other
resources can be used and some additional papers are suggested below.


Topics and Structure

This essay should be in the general style of one of the three reference
papers. It should cover the areas of design capture, design
partition and co-design. It must be called 'System-Level Design
Techniques' and it should include a worked example of your own
creation (not completely copied from somewhere).  Approximately
half of the essay should be devoted to the worked example with the
remainder being a general review.  The worked example should be any
piece of standalone electronic equipment containing embedded processors, such as
a mobile phone/PDA, engine management system or autonomous weather station.
You should describe the techniques, tools and languages used in industry
when designing and modelling such a product, with emphasis on high-level
design entry and capture.  Do not dwell on back-end processes, such
as mechanical modelling and physical design.

For marking purposes, the essay should include at least 12 of the
following topics/phrases and these should be highlighted in bold font.
Note that this topic list does NOT include anything to do with
temporal logic, assertions or declarative forms of design expression,
since these are covered in Section 3 of the course.

1. Architecture Exploration
2. Design Partition
3. XML interchange and the IP-XACT schema
4. Transactors and TLM
5. Instruction Set Simulator versus natively-compiled firmware
6. Codesign and manual design partition
7. SysML
8. State Machine or statecharts (see slide pack 3.2 next week)
9. Register and Memory Map Management
10. Automated assembly of IP blocks using Glue Logic and so on
11. UML applicabilty for hardware design
12. Textual versus GUI entry formats
13. Round Tripping (upwards propagation of modifications at lower-level)
14. Power estimation, battery life modelling
15. SystemC compared with RTL
16. Eclipse Electronic Data Book or NetBeans IDE equivalents.
17. Loose timing and transaction ordering
18. Round tripping and/or abstraction layer cross referencing
19. Rapid functional prototype
20. Symbolic debugging or RSP debug protocol

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DRAFT LIST OF Additional papers and things to try or look at:

P4. Executable Models and Verification from MARTE and SysML: a Comparative Study of Code Generation Capabilities by  Marcello Mura, Amrit Panda, Mauro Prevostini.

Install org.eclipse.dd.ipxact.feature.group in your version of Eclipse and try it!

http://www.design-reuse.com/articles/17562/high-level-sysml-systemc-soc-designs.html

www.spiritconsortium.org/press/IP-XACT_1_4_10Mar08.pdf 

http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=04484656

http://dspace.mit.edu/bitstream/handle/1721.1/46612/426039412.pdf?sequence=1