SoC D/M Proficiency Tick 3: 5 marks. SystemC/RTL. Tick 3 is a preliminary exercise in software/hardware partition. This tick can be answered relatively quickly and shortly, or else a full design with optional extensions can be handed in. There is no extra credit available for a detailed answer, but some people might find the experience enjoyable. The exercise is to partition an audio sample player into a mixture of hardware and software for implementation as part of a system-on-chip. The component plays one note at a time and a bank of them would be used in a polyphonic synthesiser. It renders a PCM-coded waveform at an appropriate pitch and envelope, where control and low-load operations (such as perhaps the envelope generation) are performed by an embedded processor, consuming no more than 5 percent of its performance. The main data movement and other operations should be performed by a custom hardware subsystem. The component is controlled by making non-blocking subroutine calls from other code assumed to be running on the same embedded processor. Typically some 20 to 60 of these components would be controlled at once by one microprocessor. See one of the 'generators' on http://www.pykett.org.uk/synths.htm#DigitalDetail Pseudo-code for a software-only version of the base functionality is provided HERE: http://www.cl.cam.ac.uk/teaching/0910/P35/tick3-pseudocode.txt but this does not meet all the design specifications. Specifications: Waveform storage capacity: 16 bits, 44100 samples per second, 5 seconds capacity. Output port: 24 bit word at 44100 words per second. Processor: 32 bit RISC-like, programmed in C or assembler, etc.. Use any mixture of programmed I/O, interrupts or DMA for h/w s/w API. For full credit, please include at least one of the following extensions to the base functionality in your answer: 1. Loop point: to extend the note duration, the stored waveform is looped back from its last sample to a designated sample position. 2. ADSR: The base functionality has a two-parameter envelope shaper, but a more typical ADSR form with four or more parameters can be implemented. 3. Sample rate conversion: the base functionality repeats and skips samples to adjust the pitch, but sample-rate conversion (e.g. by convolving with a sync response) would be better. 4. Pitch envelope: The base functionality uses a fixed pitch throughout the note whereas many real sounds are not like that (e.g.\ a mellotron) and so a second transient generator is added that modulates the pitch. Questions: 1. Sketch a block diagram of the design, explain the purpose of each block, describe fully the interfaces between the sub-components and briefly justify your decisions as to what to do in hardware and what in software. Be specific on the interface(s) between h/w and s/w components. You should give register maps and/or sufficient detail for a hardware team and a software team to work separately from your specification. 2. Give a rough calculation of the percentage load on the processor during normal operation and explain how this influences the chosen design partition. Note that low-cost embedded processors (ARM/MIPS type) have clock frequencies around 300 MHz. 3. Sketch a useful model setup that uses TLM-style communication between some of the major components. This would be used to confirm system dimensioning and for testing to capture playable audio output to a file, where the firmware for the embedded processor is pretty much complete but where the hardware is not modelled with full-cycle accuracy. Full and sensible answers to the above questions are needed for full credit. However you may find it useful, informative or interesting to develop actual code. If you decide 'everything can be done in software without any hardware' please give careful justification and a full explanation of how the residual connection to a hardware output port is made (e.g.\ S/P-DIF or DAC). END