Computer Laboratory

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Reading List For Lent Term 2017/18

Mini Seminar Papers

In the timetable for the term we shall have two mini seminars (discussion-sessions) with perhaps 4 papers in the first session and the remaining 4 in the second. Papers 2 and 5 relate to HLS and will certainly be in the second session.

  1. "Fundamental Underpinnings of Reconfigurable Computing Architectures" by DeHon. 2015. PDF.

  2. "Polyhedral Bubble Insertion: A Method to Improve Nested Loop Pipelining for High-Level Synthesis" Antoine Morvan, Steven Derrien, and Patrice Quinton. IEEE TCAD 2013. PDF.

  3. "pn: a Tool for Improved Derivation of Process Networks" Sven Verdoolaege, Hristo Nikolov, Todor Stefanov. 2007. PDF.

  4. "Measuring the Gap Between FPGAs and ASICs" Ian Kuon and Jonathan Rose, 2006. (Also in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 2, pp. 203-215, 2007.) PDF.

  5. "LP-HLS: Automatic power-intent generation for high-level synthesis based hardware implementation flow." Qamar et al 2017 PDF.

  6. "Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks" by Chen Zhang et al. 2015. PDF.

  7. "Thousand Core Chips—A Technology Perspective" Shekhar Borkar at DAC'07. PDF.

  8. "When FPGAs are better at floating-point than microprocessors." Florent de Dinechin et al. 2007. PDF.

General Reading

The following resources will be generally useful as background for the course practical work:

  1. Reconfigurable Hardware Accelerators: Opportunities, Trends, and Challenges by Chao Wang et al 2017. LINK

  2. There is a collection of System On Chip Lecture Notes on this link: SoC Design and Modelling Patterns (PDF). Some of this material will be lectured as part of the P35 ACS module but most of it is lecture notes given to undergraduates in recent years.

  3. Xilinx Zync Product Brief Xilinx Ultrascale MP-SoC.

  4. Conservation Cores: Reducing the Energy of Mature Computations. ASPOLOS'10. Ganesh Venkatesh, Jack Sampson, Nathan Goulding, Saturnino Garcia, Vladyslav Bryksin, Jose Lugo-Martinez, Steven Swanson, Michael Bedford Taylor. Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. In this regime, specialized, energy-efficient processors can increase parallelism by reducing the per-computation power requirements and allowing more computations to execute under the same power budget. To pursue this goal, this paper introduces conservation cores. Conservation cores, or c-cores, are specialized processors that focus on reducing energy and energy-delay instead of increasing performance. This focus on energy makes c-cores an excellent match for many applications that would be poor candidates for hardware acceleration (e.g., irregular integer codes). We present a toolchain for automatically synthesizing c-cores from application source code and demonstrate that they can significantly reduce energy and energy-delay for a wide range of applications. The c-cores support patching, a form of targeted reconfigurability, that allows them to adapt to new versions of the software they target. Our results show that conservation cores can reduce energy consumption by up to 16.0x for functions and by up to 2.1x for whole applications, while patching can extend the useful lifetime of individual c-cores to match that of conventional processors. PDF.

  5. Applying Agile Techniques to IC Design. Luke Collins. LINK and "A Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services" ISCA2014 Andrew Putnam et al PDF.

  6. `High-level synthesis of dataflow programs for heterogeneous platforms : design flow tools and design space exploration' Endri Bezati, 2015 PDF.

  7. ... TBD

  8. ... TBD

Reading lists from previous years are here: OLD READING LISTS.


© David Greaves 2018.