BERI (and CHERI) are accompanied by a number of technical reports documenting their design, implementation, and use, both from hardware and software development perspectives.
- Bluespec Extensible RISC Implementation: BERI Hardware reference (UCAM-TR-868)
- An introduction to the BERI CPU, getting started guide for configuring your environment and running the CPU in simulation, details of the CPU architecture for BERI1 and BERI2, instruction set architecture (ISA), description of hardware peripherals on the DE4 board. (Previous version UCAM-TR-852)
- Bluespec Extensible RISC Implementation: BERI Software reference (UCAM-TR-869)
- Guide to building FreeBSD/beri and booting, both in simulation and on the DE4 board. (Previous version UCAM-TR-853)
- Capability Hardware Enhanced RISC Instructions: CHERI User’s guide (UCAM-TR-851)
- The User’s Guide is targeted at hardware and software developers working with capability-enhanced software. It describes the CheriBSD operating system, a version of the FreeBSD operating system that has been adapted to support userspace capability systems via the CHERI ISA, and the CHERI Clang/LLVM compiler suite. It also describes the earlier Deimos demonstration microkernel.
- Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture (UCAM-TR-864)
- This report describes the CHERI architecture and design, and provides reference documentation for the CHERI instruction-set architecture (ISA) and potential memory models, along with their requirements. It also documents our current thinking on integration of programming languages and operating systems. (Previous version UCAM-TR-850)
This hardware, software, and documentation was developed by SRI International and the University of Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research programme. Additional support was received from Google.