# Computer Laboratory

Course pages 2015–16

# ECAD and Architecture Practical Classes

## Tick 1

To achieve Tick 1 you need to:

• Answer the following questions on screen or on paper, and show them to a demonstrator
• Show a demonstrator your rotary encoder and division code on screen or on paper
• Show the demonstrator your working Etch-A-Sketch in simulation

To achieve a starred Tick 1 you can show a demonstrator Pong in simulation instead of Etch-A-Sketch.

### Questions

1. The following SystemVerilog might not do what the designer intended. Identify some of the pitfalls they fell into:

```// a module containing two 8-bit counters
// If latch is high, we store and output the two 8-bit counter values
// If latch is not high, the two outputs swap on each clock cycle

module alternating_counters(
input clock,
input reset,
input latch,
output logic out_a,
output logic out_b
);

logic [7:0] count_a;
logic [7:0] count_b;

initial begin
count_a <= 8'h0;
count_b <= 8'h80;
end

always @(clock) begin

count_a <= count_a - 1;
count_b <= count_b + 1;

out_b = latch ? count_b : out_a;
out_a = latch ? count_a : out_b;

end

endmodule
```
(if you get stuck, try it in ModelSim)
2. The Yarvi has separate address spaces for instructions and data. What limitations does this cause in practice?
3. How efficient is your division routine? Derive an expression for the number of cycles it takes based on the number of bits in a0 and a1. It doesn't matter if your expression is inexact. (Hint: using your simulation first measure the baseline, the smallest number of cycles it takes for example when a0=0. Then add in other term(s))

### Procedure

You will need to hand in your results as part of your Portfolio of Assessed Laboratory work in Easter term, so keep them safe. You should hand in:

```Name of practical class and tick: ECAD+Arch tick 1