Department of Computer Science and Technology

Technical reports

Bluespec Extensible RISC Implementation: BERI Hardware reference

Robert N.M. Watson, Jonathan Woodruff, David Chisnall, Brooks Davis, Wojciech Koszek, A. Theodore Markettos, Simon W. Moore, Steven J. Murdoch, Peter G. Neumann, Robert Norton, Michael Roe

April 2014, 76 pages

Sponsored by the Defense Advanced Research Projects Agency (DARPA) and the Air Force Research Laboratory (AFRL), under contract FA8750-10-C-0237 (“CTSRD”) as part of the DARPA CRASH research program. The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense.

DOI: 10.48456/tr-852


The BERI Hardware Reference documents the Bluespec Extensible RISC Implementation (BERI) developed by SRI International and the University of Cambridge. The reference is targeted at hardware and software developers working with the BERI1 and BERI2 processor prototypes in simulation and synthesized to FPGA targets. We describe how to use the BERI1 and BERI2 processors in simulation, the BERI1 debug unit, the BERI unit-test suite, how to use BERI with Altera FPGAs and Terasic DE4 boards, the 64-bit MIPS and CHERI ISAs implemented by the prototypes, the BERI1 and BERI2 processor implementations themselves, and the BERI Programmable Interrupt Controller (PIC).

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BibTeX record

  author =	 {Watson, Robert N.M. and Woodruff, Jonathan and Chisnall,
          	  David and Davis, Brooks and Koszek, Wojciech and Markettos,
          	  A. Theodore and Moore, Simon W. and Murdoch, Steven J. and
          	  Neumann, Peter G. and Norton, Robert and Roe, Michael},
  title = 	 {{Bluespec Extensible RISC Implementation: BERI Hardware
  year = 	 2014,
  month = 	 apr,
  url = 	 {},
  institution =  {University of Cambridge, Computer Laboratory},
  doi = 	 {10.48456/tr-852},
  number = 	 {UCAM-CL-TR-852}