ECAD and Architecture Practical Classes

Tick 1 - Up/Down Counter

Let's try out some of the SystemVerilog you have learnt.

The task is to design an 4-bit counter that counts up when the up input is high, otherwise it counts down. Below is an outline module. Since this design only requires a few lines of code, we can design and test it using the Moodle ticker. Your code should use the rst signal to reset count to zero when rst is high.

Note that you can complete this tick just using Moodle, but it is also worth having a go at simulating the design using one of the methods in Setup.

Outline module

module updowncounter
  (
   input logic        clk,
   input logic        rst,
   input logic        up,
   output logic [3:0] count
   );

   // insert your code here

endmodule