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Part II CST SoC D/M Slide Pack 7 (Tools/Tech/Eng)

  • SoC Engineering and Associated Tools
  • Static Timing Analyser Tool
  • RAM Macrocell Compiler Tool
  • Test Program Generator Tool
  • Scan Path Insertion and JTAG standard test port.
  • Architectural Design Exploration
  • H/W to S/W Interfacing Techniques
  • Conservation Cores Approach
  • H/W Design Partition
  • Chip Types and Classifications
  • IC Taxonomy
  • Semi-custom (cell-based) Design Approach
  • Cell Library Tour
  • Gate Arrays and Field-Programmable Logic.
  • FPGA - Field Programmable Gate Array
  • PALs and CPLDs
  • H/W versus S/W Design Partition Principles
  • An old partitioning example: An external RS-232/POTS Modem.
  • Partitioning example: A Bluetooth Module.
  • ASIC costing.
  • Structured ASIC
  • Xilinx Zynq Super FPGA
  • Silicon Power and Technology
  • Deep submicron and Dark Silicon
  • Semi-Custom Design (Repeated Slide)
  • 90 Nanometer Gate Length.
  • Delay Estimation Formula.
  • Power Estimation Formula
  • 45nm SRAM Memory Area and Power Consumption
  • Power Consumption Example
  • Save Power 1: Dynamic Clock Gating
  • Save Power 2: Dynamic Supply Gating
  • Save Power 3: Dynamic Frequency Scaling
  • Save Power 4: Dynamic Voltage Scaling
  • Future Trends
  • Power Modelling using SystemC
  • SAIF Files
  • TLM POWER 3 library for SystemC: SRAM example