This section may not be lectured since PALs are no longer important.
Programmable Array Logic and CPLDs (Complex Programmable Logic Devices) achieve very low delay in return for simple, nearly fixed, wiring structure.
All expressions are expanded to SOP form with limited number of products.
pin 16 = o1; pin 2 = a; pin 3 = b; pin 4 = c o1.oe = ~a; o1 = (b & o1) | c; -x-- ---- ---- ---- ---- ---- ---- (oe term) --x- x--- ---- ---- ---- ---- ---- (pin 3 and 16) ---- ---- x--- ---- ---- ---- ---- (pin 4) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx x (macrocell fuse)