The cost of a chip divides into two parts: NRE and per-device cost.
|Item||Cost (KUSD)||Total (KUSD)|
|6 months : 10 H/W Engineers||250 pa||1250|
|12 monts : 20 S/W Engineers||200 pa||4000|
|1 Mask set (45nm)||3000||3000|
|n 8 inch wafers||5||5n|
|TOTAL||5||8125 + 5n|
For small quantities: share cost of masks with other designs e.g. MOSIS offers multiproject wafer (MPW).
The fraction of wafers where at least some of the die work is the `wafer yield'. Historically yields have been low, but was typically close to 100 percent for mature 90 nm fabrication processes, but has again be a problem with smaller geometries in recent years. The fraction of die which work on a wafer (often simply the `yield') depends on wafer impurity density and die size. Die yield goes down with chip area.
The fraction of devices which pass wafer probe (i.e.~before the wafer is diced) and fail post packaging tests is very low. However, full testing of analog sections or other lengthy operations are typically skipped at the wafer probe stage. Assume processed wafer sale price might be 5000 dollars:
|Area||Wafer dies||Working dies||Cost per working die|