The average SoC is 71 percent RAM memory. The RAMs are typically generated by a RAM compiler. The input parameters are:
The outputs are a datasheet for the RAM, high and low detail simulation models and something that turns into actual polygons in the fabrication masks.
// Low-level model (RTL) for a RAM. Example 1.
module R1W1RAM(din, waddr, clk, wen, raddr, dout);
input clk, wen;
input [14:0] waddr, raddr;
input [31:0] din;
output [31:0] dout;
// Mem array itself: 32K words of 32 bits each.
reg [31:0] myram [32767:0];
always @(posedge clk) begin
dout <= myram[raddr];
if (wen) myram[waddr] <= din;
end
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// Low-level model (RTL) for a RAM. Example 2.
module R1W1RAM(din, addr, clk, wen, dout);
input clk, wen;
input [14:0] addr;
input [31:0] din;
output [31:0] dout;
// Address register: latency of 1 one cycle.
reg [14:0] addr1;
// Mem array itself: 32K words of 32 bits each.
reg [31:0] myram [32767:0];
always @(posedge clk) begin
addr1 <= addr;
if (wen) myram[addr1] <= din;
else dout <= myram[addr1];
end
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// Example high-level model for both RAMs // This RAM model has a pair of entry points
SC_MODULE(R1W1RAM) // for reading and writing.
{ // It also has a TLM convenience socket
uint32_t myram [32768]; // which would decode a generic payload and
int read_me(int A) { return myram[A]; } // call one or other of those entry points
write_me(int A, int D) { myram[A] = D; } // for each transaction.
tlm_utils::simple_target_socket port0;
...
Sometimes self test modules are also generated. For example Mentor's MBIST Architect(TM) generates an SRTL BIST with the memory and ARM/Artisan's Generator will generate a wrapper that implements self repair of the RAM by diverting access from a fault row to a spare row. »ARM Artisan
Other related generator tools would be similar in use: e.g. a FIFO generator would be similar and a masked ROM generator or PLA generator.