CMOS delay is inversely proportional to supply voltage.
Voltage to a region may be varied dynamically. A higher
Operating region of the frequency/voltage curve is roughly linear.
But, logic with higher-speed capabilities is smaller which means it
Let's only raise VCC when we ramp up f.
But Zeno applies still: always aim for 'a' as high as possible and minimal halt cycles.
Overall: power will then have cubic dependence on f. So we achieve peak performance under heavy loads and avoid cubic overhead when idle.
So a typical SoC uses not only many dynamic clock gated islands, but also some sub-continents with automatic frequency and voltage variation.
Power isolation originally used on a longer and larger scale (complete continents) but now a lot of power islands are being used.
For 45nm and smaller, voltage scaling may not be possible and static leakage may be very high: so clock within the frequency band that works and then power off until next deadline.