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Save Power 4: Dynamic Voltage Scaling

CMOS delay is inversely proportional to supply voltage.

Voltage to a region may be varied dynamically. A higher
supply voltage (at fixed f) uses more power (square law) but allows a higher f.

Operating region of the frequency/voltage curve is roughly linear.

But, logic with higher-speed capabilities is smaller which means it
(generally) consumes greater leakage current which is being wasted while we are halted.

Let's only raise VCC when we ramp up f.


  1. Adjust f for just-in-time completion (e.g. in time to decode the next frame of a real-time video),
  2. then adjust VCC so logic just works.

But Zeno applies still: always aim for 'a' as high as possible and minimal halt cycles.

Overall: power will then have cubic dependence on f. So we achieve peak performance under heavy loads and avoid cubic overhead when idle.

So a typical SoC uses not only many dynamic clock gated islands, but also some sub-continents with automatic frequency and voltage variation.

Power isolation originally used on a longer and larger scale (complete continents) but now a lot of power islands are being used.

For 45nm and smaller, voltage scaling may not be possible and static leakage may be very high: so clock within the frequency band that works and then power off until next deadline.

54: (C) 2008-12, DJ Greaves, University of Cambridge, Computer Laboratory.