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ACS P35-10/11 SoC D/M Slide Pack 1.1 (RTL)

  • SoC Design and Modelling
  • Syllabus
  • Classes and Coursework Assessments

    Introduction: What is a SoC ?

  • Introduction: What is a SoC ?
  • Design Flow
  • Design Flow Diagram
  • Levels of Modelling Abstraction

    Review/Revision of Verilog RTL

  • Review/Revision of Verilog RTL
  • RTL Summary View of Variant Forms.
  • Structural Verilog
  • Structure Flattening
  • 2a/3: Continuous Assignment.
  • 2b/3: Pure RTL : unordered register transfers.
  • Elementary Examples
  • 3/3: Behavioural RTL
  • Simulation And Synthesis.
  • SRTL abstract syntax
  • Behavioural - `Non-Synthesisable' RTL
  • Structural Hazards.
  • Structural Hazards in RTL
  • Folding, Retiming & Recoding
  • Critical Paths
  • Protocol and Interface
  • Transactional Handshaking
  • Transactional Handshaking in RTL (Synchronous Example)
  • RTL Compared with Software
  • Further Synthesis Issues
  • RTL Conclusion

    Adder & Multiplier Structures.

  • Adder & Multiplier Structures.
  • Adder Build (Synthesis)
  • Kogge Stone adder
  • Subtractor, Equality, Inequality, Shifts
  • Long Multiplication
  • Micro-Architecture for a Long Multiplier
  • Booth's Multiplier
  • Shifters

    Event Driven Simulation Kernel

  • Event Driven Simulation Kernel
  • Toy implementation of EDS RTL Simulator.
  • Modelling Zero-Delay Components
  • Compute/Commit Cycle With Delta Cycles
  • Toy implementation of RTL Synthesiser
  • Basic RTL Synthesis Algorithm
  • Examples of converstion to binary (bit lane) form
  • RTL Synthesis: Summary