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Non Determinism.

If we have the following:

  always @(posedge clk) v <= 1;
  always @(posedge clk) v <= 0;

we have a non-deterministic design (banned for synthesis).

Exercise: Here's a more interesting example:

  always @(posedge clk) begin
     v1 = v1 + 10;
     v2 = v3;
     end

  assign v3 = v1 + 1;

What happens here: does the continuous assignment get executed between the assignments of v1 and v2 ?

Toy implementation of RTL Synthesiser

How do we compile synthesisable RTL to gates?

Example input:

module TC(clk, cen);
  input clk, cen;
  reg [1:0] count; 
  always @(posedge clk) if (cen) count<=count+1;
endmodule// User=djg11

Output:

module TC(clk, cen);
  wire u10022, u10021, u10020, u10019;
  wire [1:0] count;
  input cen;   input clk;
  CVINV  i10021(u10021, count[0]);
  CVMUX2  i10022(u10022, cen, u10021, count[0]);
  CVDFF  u10023(count[0], u10022, clk, 1'b1, 1'b0, 1'b0);
  CVXOR2  i10019(u10019, count[0], count[1]);
  CVMUX2  i10020(u10020, cen, u10019, count[1]);
  CVDFF  u10024(count[1], u10020, clk, 1'b1, 1'b0, 1'b0);
endmodule