Toy versions of two RTL processing algorithms are described in this section:
Gate-level generators for multipliers, adders, shifters, checkers and other low-level operators is given elsewhere.
Datastructure for the model (flattened netlist form):
(* A net has a string name and a width. * A net may be high z, dont know or contain an integer from 0 up to 2**width - 1. * A net has a list of driving and reading models. * A model has a unique instance name, a delay, a form and a list of nets it contacts. * It also may have some internal state, held in the last field. *) datatype value_t = V_n of int | V_z | V_x; datatype m_t = M_AND | M_OR | M_INV | M_XOR | M_DFF | M_BUFIF | M_TLATCH | M_CLOCK; datatype internal_state_t = IS_NONE | IS_DFF of value_t ref | IS_CLOCK of int ref ; datatype net_t = NET of value_t ref * string * int * model_t list ref * model_t list ref and model_t = MODEL of string * int * m_t * net_t list * internal_state_t ;
This form of model requires the leaf components (gates) to be built in to the simulator with hard-coded behaviour.
Another form of model, derived originally from Simula in the 1960s, uses user-coded leaf models to be implemented using an imperative language that is interpreted by the simulator.
Verilog RTL supports both built-in gate models and modelling with behavioural threads. par SystemC has no built-in models.