An enhancement is needed when zero-delay models are present because new events generated by such models can also be at time tnow: at a minimum, we need to insert them after all other events with time tnow.
The common solution is to implement delta cycles using the compute/commit paradigm, whereby all new events are generated as pending updates, waiting to be committed, but the commit is not done while there are still events with time tnow on the event queue.
VHDL and Verilog RTL and SystemC all support the compute/commit paradigm (also known as evaluate/update). A net that is to have its updated deferred in VHDL (and SystemC) is called a signal. In Verilog, all nets can be assigned in either way and instead two different assignment operators are provided (called blocking and non-blocking).
Delta cycle: a compute/commit cycle without advancing global time.
Commit may create further events for current simulation time.
A VHDL `signal' has a current and a next value. A SystemC `sc_signal' likewise has a current and a next value. In Verilog, as said above, it's a matter of the assignment operator rather than the net declaration.