NEXT (Structural Hazards in RTL Continued)
Structural Hazards in RTL
A structural hazard in an RTL design can make it non synthesisable.
Consider the following expressions:
q <= Foo[x] + Foo[y];
q <= Foo[Foo[v]];
q <= a*b + c*d;
(A flash multiplier is a combinational circuit that computes in less than one clock cycle).
- The RAM or register file Foo might not have two read ports.
- Even with two ports, can it perform the double subscription in one clock cycle?
- The cost of providing two 'flash'
multipliers for use in one clock cycle while they lie idle
much of the rest of the time is likely not warranted.
In addition, the RAMs may be synchronous with fixed latency
and the multiplication time might be data dependent.
The multipliers might not be fully-pipelined.