An RTL program can be used both for simulation and synthesis.
Simulation: uses event-driven simulation (EDS). When using zero-delay models, we use the compute/commit paradigm where the EDS kernel is augmented to support delta cycles.
Synthesis: involves converting to a parallel form with one right-hand-side expression per variable. Then converting each expression to a logic tree, preferably taking into account sub-expression sharing and user speed/power/area requirements.
Simulation uses a top-level test bench module with no inputs.
Synthesis runs are made using points lower in the hierarchy as roots.
Synthesisable code uses synthesisable subset!