Course material 2010–11
This course aims to teach students how to design processors, starting with the Verilog hardware description language and proceeding onto the hardware/software processor interface and processor design implementation issues.
- Harris, D.M. & Harris, S.L. (2007). Digital Design and Computer Architecture. Morgan Kaufmann.
- Hennessy, J.L. & Patterson, D.A. (2002). Computer Architecture: A Quantitative Approach. Morgan Kaufmann (3rd ed.).
- Hennessy, J.L. & Patterson, D.A. (1998). Compuer Organization and Design. Morgan Kaufmann (2nd ed., as an alternative to the above).
Handouts and practicals
- Copies of the handouts will be made available at the first lecture and subsequently from the Student Administrator at the Computer Laboratory. Please note that the handouts only give an outline of the course. Annotations and additional examples are given in the lectures.
- If paper copies of the handouts are not available for some reason, the PDF of the notes is here for people inside the cam.ac.uk domain.
- Exercise sheet (PDF) which whould be completed in full
- ECAD+Architecture workshops (the practical component to this course)
- Manchester Baby machine in SystemVerilog and Java: see the EACD+Arch page on the Baby
- Simplified MIPS processor simulated in Java: java-mips-simulator.zip
- Simplified MIPS processor in Verilog: simplemips.zip (unzip to
U:\simplemips\ since some paths in the project are absolute)
- Quick start to simulate using ModelSim...Start ModelSim and then:
- open project simplemips.mpf in the above zip file
- compile -> compile all
- simulate -> Start Simulation..., select work.testBench to simulate, click OK
- simulate -> Run -all
- For further information see the tutorial on ModelSim
Links used in Lecture 10:
- Intel Nehalem processor
- Video at Intel - see "Behind the Schenes" -> "Virtial Tour of Intel's 45nm Factory"
- MIPS32 quick reference
- Interesting paper highlighting the current challenges: "The Future of Microprocessors - Energy efficiency is the new fundamental limiter of processor performance, way beyond numbers of processors.", Shekhar Borkar, Andrew A. Chien, Communications of the ACM Vol. 54 No. 5, Pages 67-77, 10.1145/1941487.1941507
- ARM white paper on the Jazelle DBX acceleration of Java Byte Codes
- EDSAC Movie
- EDSAC simulators
- CPU Info Center
- Computer History Museum
- Virtual museum of computing (alternative link)