ACS P35 Persistent Course Material

Reading List for 2013

Reading list is on this page: Reading List.

Local Online Resources

Design and Layout of 8-bit Kogge Stone Adder 8 Pages (PDF).
MOSIS AMI 0.5 micron Cell Library 98 Pages (PDF).

Local Online Resources (For ACS)

Set up paths and find local resources using TOOL INFO
Documents and Reference Materials (members of Computer Lab only) DOCUMENTS FOLDER.
Online magazine: DESIGN AND REUSE.
THE MATERIAL BELOW THIS LINE DATES FROM 2011-12 AND IT MAY BE EDITED AS WE PROCEED.
In general: please read through the next set of slides in advance of the lecture session and be prepared to say which bits you want lectured in detail. If this is all of it then that's ok!
Preparatory Work (SystemC): Please become familar with this material over the Michaelmas Vacation 2012 so that it can be covered fairly rapidly in the first week (or two) of the Lent Term 2013: PREPARATION.
LG 1 slides (not all will be used): 1.1-RTL, 1.2-SystemC-Basic, 1.3-SoC-Parts-RTL.
LG 2 slides: 2.0-TOY-ESL, 2.1-ESL,
LG 4 slides: 4.1 Bus NoC - I'll just present the switch fabrics quickly so we can discuss contention modelling, then the DRAM slides, 4.2 Power.
LG 3 slides (lectured after LG4): 3.2 Higher-level design etc.(HLS), 3.1 Assertion-Based Design (ABD).

Practical Systems

Toy ESL System

Please first become familiar with this very simple system. It is a stepping stone to the main OR1200 system: TOY ESL. It can be copied from the filesystem at /usr/groups/han/clteach/socdam/toyclasses.

Main OR1200 Blocking TLM Testbed

We will use this blocking TLM implementation as the basis for the majority of the exercises.

The main binary of the simulator is or1ksmp in /usr/groups/han/clteach/btlm-baseline/openrisc/testbench.
The simplest application is hello world without using libc, found in /usr/groups/han/clteach/btlm-baseline/openrisc/sw/hello-world.
A more interesting application is a machine code monitor found in /usr/groups/han/clteach/btlm-baseline/openrisc/sw/mixbug
Other applications and the SPLASH-2 benchmarks and the linux kernel can also be run if you like. Please ask.

Investigations for 2013

Single-core algorithms are not the best on parallel architectures? We shall investigate how well the textbook algorithms work on contemporary and future architectures:
- Tree Quicksort (Guy Belloch, CMU) ML FORM.
- Polyphase radix sort. From the SPLASH benchmarks.
Virtual machine versus real machine - what takes the most power when L1 I-cache struggles ? I will provide you with an application program coded in three ways: bytecode for the dotnet VM, a natively compiled version and a compiled to gates form. Which uses the least power or scales the best as cores are added? Is it worth having hardware support for the dotnet VM ?
Repeat last year's exercise (power consumption for CRC co-processor compared with software).

Other (sketchy) Investigations for 2013

These are some of my research ideas that we can perhaps take further as exercises? Basically you will explore the behaviour of some application as it is partitioned differently: using various processor cores or hardware assist. You will perhaps be allocated tasks in pairs, with one writing the hardware and the other the software. This means you have to agree on the specification in advance.

RTL is King ? The King is dead? For too long RTL has been the narrow waist of chip design, connecting the back-end flow to the front-end flow. Can we do place and route while re-pipelining the design ?
Single-core algorithms are not the best on parallel architectures? We shall investigate how well the textbook algorithms work on contemporary and future architectures:
- Dijkstra's shortest path? Best for parallel?
- Bloom filter Best for parallel?
Anomalies in the ASUS mother board power probe? Can we get to the bottom of it (needs a kernel hacker)?

Computer Laboratory