psfig

FPC2 xilinx chip - Xi3
Design and Software

Mark Hayter and Richard Black

10th March 1994

Following the initial experiments on the FPC2 the port controller xilinx chip was redesigned resulting in the ``Xi3'' design. This document describes the interface of the Xi3 chip, and the current Wanda driving software. This version is the one typically currently used on the FPC2. The Xi4 design is a derivative used only for hardware testing and Xi4 bits should not be used in any port controllers. The Xi6 design is a retro fit of some of the compatibility fixes of Xi5 to the X3 design. At the date of writing the Xi6 design is less used mostly because of a lack of software support.

• Changes made for Xi3 xilinx
• The Cell Buffer
• The queue
• Registers
• ARM accesses
• Interrupts
• Known problems with the Xi3 bits
• The interrupt handler
• Performance
• About this document ...