The Xi3 timing out of cells has caused problems when correct but slow cells are recieved. This is seen for example when the source is a ``Yes'' board using PIO on its transmit side. There is a version of Xi3 with timing out disabled, it is intended that one be generated where two frame pulses have to occur between incomming bytes to generate a timeout.
The currently used versions of the Xi3 bits (which all appear to operate at 18 MHz) are:
