Three separately maskable FIQ interrupts may be signaled by the xilinx to IOC. Table 3 gives the IOC FIQ bit details. The Error interupt is raised if the transmission system stops (because of a reset or NACK) or the free queue becomes empty. The IrqStat register may be read to determine the cause of the error. For the meaning of the other bits in this register see the general port controller document.
Table 3: IOC FIQ Status register