The processor interface is based on the ``slowarm'' interface developed for the previous version of the xilinx design. This ensures resynchronisation at all possible points and thus allows any combination of processor and fabric clock speeds. This is done at the expense of making accesses a minimum of three processor REF8M cycles.
The access address is (incompletely) decoded to give access to the buffer SRAM and the xilinx registers. Tables 1 and 2 give the addresses used to decode read and write accesses.
Write accesses to a register use address bits to select which register is written, by setting more than one of these bits several registers may be written (with the same value) in one cycle.
The processor has to setup the queue structure before starting the xilinx chip. The chip resets with all registers equal to zero and transmission stopped. HeadP will be equal to TP1 so reception is also disabled. Thus the last step of the initialisation code is to set HeadP and issue a ``GoTx'' command. The processor must save the buffer number of the tail of the transmission list since this information is not stored anywhere else.
To transmit a buffer the processor should check that there are transmit slots available. When there are the new buffer is added to the transmit queue by writing its buffer number and transmit flags into the link word of the transmission tail - this write should have the ``increment CNT'' bit set in its address. A write with increment when the transmit queue is full will not change CNT, but will modify memory, if this happens things are likely to go wrong.
When a receive interrupt is seen the buffer number may be obtained by reading the value of ArmP. If this read is done with reload then ArmP will be moved to the next queue entry, and the receive interrupt bit will be updated. Since a reload is only performed if there was a buffer to be collected it is safe to do a read-with-reload of the IrqStat/ArmP register at the start of an ISR, allowing a single read to determine both the interrupt reason and collect the next buffer.
