Changes made for Xi3 xilinx

The Xi3 xilinx chip for the port controller is almost a complete rewrite of the hardware from the earlier Xi2 device. There has been some ``cut and paste'' from the previous design, and some libraries are common, but most of the HDL files have been completely rewritten. The main noticable changes are:

• The system of transmit and receive queues in cell buffer 0 has been replaced by a single linked list, managed by the hardware.

• Data bus D[0..15] and D[30..31] are taken into the xilinx. These provide access to several registers.

• The status register has been replaced. Decoding of the address bus allows selection of what status information is to be read. In particular the interrupt request bits and the received buffer number may be read in a single operation.

• The arbiter has been changed (again). The word2fabric section now demands memory access. In other cycles the arm and fifo2word section get alternately offered use of memory. If the fifo2word section uses the offered cycle then it will not be offered memory in the next four cycles since it is known that it will not use them. A hacked up simulation indicates that this policy fractionally increases the expected wait for arm and f2w accesses if data is being moved at full speed. It makes the design simpler so Im going to do it, as it can always be changed later.

• The transmit buffer number now includes a retry count. The cell will be retried on NACK until the number of NACKs is equal to the retry count when the transmission system stops and interrupts.

• Only the ``slowarm'' interface is used.

• The rx jam condition has been fixed. Cells that do not come in fast enough are timed out.

• The NACK control logic has been put in a single module so different versions can be easily tried.

• A timestamp is put in word 0 of every rx cell. This has an 11 bit count which increments on every frame pulse, and also includes source information.

• A transmit cell can be marked for return to free queue without transmission. Note this process still takes a frame time.

• A cell can be requested from the free queue. It is marked by a bit in the VCI.

• The ``goXilinx'' strobe is done by writing a bit in the command register - this needs only one write rather than two through IOC. The IOC method is no longer possible.

• The detection of empty fifos has been changed. In particular the metastable state caused by the fifo briefly becomming empty should be less of a problem.