The cell buffers fall into four classes: waiting collection by the reception FIQ, on the free queue, on the transmit queue, and being used by software. The cell buffers in the first three classes are linked together by cell buffer numbers in their link field (currently word 14). These form a single list with pointers in the xilinx chip marking the boundaries as shown in figure 2.
Figure 2: New xilinx queue structure.
The queue must be set up by the processor before starting the xilinx. The queue is automatically maintained because the processor adds buffers for transmission to the tail. Once these are sent they form part of the free queue before being used for reception. Buffers not in the queue are assumed in use by software, and must be entirely managed by software. This works well while the processor is not a net source or sink of cells. Methods exist for doing fake transmissions and receptions to allow software to correct any imbalance.