| Category | Subcategory | Test Name | Allow? |
|---|---|---|---|
| Aliasing | Coherence | CoRR0.alias+po | ⤫ |
| Aliasing | Coherence | CoRR2.alias+po | ⤫ |
| Aliasing | Coherence | CoWR.alias | ⤫ |
| Aliasing | Write-Forwarding | PPOCA.alias | ✓ |
| Aliasing | Out-of-order reads | RSW.alias | ✓ |
| Aliasing | Out-of-order reads | RDW.alias | ⤫ |
| Aliasing | Out-of-order reads | CoWW.alias | ⤫ |
| Aliasing | Out-of-order reads | MP.alias3+rfi-data+dmb | ✓ |
| Writing new entries | Translation tables as data memory | CoWR.inv | ⤫ |
| Writing new entries | Making a new entry | CoWTf.inv+po | ✓ |
| Writing new entries | Making a new entry | CoWTf.inv+dsb-isb | ⤫ |
| Writing new entries | Creating a new entry for another core | S.T+dmb+po | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv+dmb+dsb-isb | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv+dmbs | ✓ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv+dmb+ctrl-isb | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv+dmb+addr | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv+dmb+po | ✓ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+po | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+dmb | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+addr | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+data | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv+dmb+data | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+ctrl | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+dsb-isb | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+ctrl-isb | ⤫ |
| Writing new entries | Creating a new entry for another core | MP.RTf.inv.EL1+dsb-tlbiis-dsb+poap | ⤫ |
| Writing new entries | Creating a new entry for another core | LB.TT.inv+pos | ⤫ |
| Writing new entries | Creating a new entry for another core | S.RTf.inv.EL1+dsb-tlbiis-dsb+data | ⤫ |
| Writing new entries | Creating a new entry for another core | S.RTf.inv.EL1+dsb-tlbiis-dsb+ctrl | ⤫ |
| Writing new entries | Creating a new entry for another core | S.RTf.inv.EL1+dsb-tlbiis-dsb+dmb | ⤫ |
| Writing new entries | Creating a new entry for another core | S.RTf.inv.EL1+dsb-tlbiis-dsb+popl | ⤫ |
| Writing new entries | Creating a new entry for another core | S.RTf.inv.EL1+dsb-tlbiis-dsb+poap | ⤫ |
| Writing new entries | Coherence | CoTW1.inv | ⤫ |
| Writing new entries | Coherence | CoTTf.inv+dsb-isb | ⤫ |
| Writing new entries | Coherence | CoTTf.inv+po | ✓ |
| Writing new entries | Coherence | CoTfT+dsb-isb | ✓ |
| Writing new entries | Coherence | CoRpteTf.inv+dsb-isb | ⤫ |
| Writing new entries | Coherence | CoRpteTf.inv+dsb | ✓ |
| Writing new entries | Coherence | CoRpteT+dsb-isb | ✓ |
| Writing new entries | Coherence | CoRpteT.EL1+dsb-tlbi-dsb-isb | ⤫ |
| Writing new entries | Coherence | CoRpteT.EL1+dsb-tlbi-dsb | ✓ |
| Writing new entries | Coherence | CoTRpte.inv+dsb-isb | ⤫ |
| Writing new entries | Coherence | CoTfRpte+dsb-isb | ⤫ |
| Writing new entries | Coherence | CoTfRpte+po | ⤫ |
| Writing new entries | Coherence | CoTfRpte+eret | ⤫ |
| Writing new entries | Coherence | CoTfW.inv+dsb-isb | ⤫ |
| Writing new entries | Coherence | CoTfW.inv+po | ⤫ |
| Writing new entries | Coherence | PPODA.RT.inv | ⤫ |
| Writing new entries | Write-forwarding | MP.RT.inv+dmb+ctrl-trfi | ⤫ |
| Writing new entries | Write-forwarding | MP.RT.inv+dmb+addr-trfi | ⤫ |
| Unmapping memory and TLB invalidation | Same-thread unmap | CoWinvT+dsb-isb | ✓ |
| Unmapping memory and TLB invalidation | Same-thread unmap | CoWinvT.EL1+dsb-tlbi-dsb | ✓ |
| Unmapping memory and TLB invalidation | Same-thread unmap | CoWinvT.EL1+dsb-tlbiis-dsb | ✓ |
| Unmapping memory and TLB invalidation | Same-thread unmap | CoWinvT.EL1+dsb-tlbiis-dsb-isb | ⤫ |
| Unmapping memory and TLB invalidation | Same-thread unmap | MP.RT.EL1+dsb-tlbiis-dsb+dsb-isb | ⤫ |
| Unmapping memory and TLB invalidation | Same-thread unmap | RBS+dsb-tlbiis-dsb | ⤫ |
| More TLB invalidation | TLBI-pipeline interactions | MP.RT.EL1+dsb-tlbiis-dsb+dmb | ⤫ |
| More TLB invalidation | Thread-local TLBIs | CoWinvT.EL1+dsb-tlbi-dsb-isb | ⤫ |
| More TLB invalidation | Thread-local TLBIs | MP.RT.EL1+dsb-tlbi-dsb+dsb-isb | ✓ |
| More TLB invalidation | Thread-local TLBIs | MP.RT.EL1+dsb-shootdown-dsb+dsb-isb | ⤫ |
| More TLB invalidation | Multiple locations | MP.RTT.EL1+dsb-tlbiis-tlbiis-dsb+dsb-isb | ⤫ |
| Stage~1 Re-mapping and break-before-make | Break-before-make | BBM+dsb-tlbiis-dsb | ✓ |
| Stage~1 Re-mapping and break-before-make | Break-before-make | BBM.Tf+dsb-tlbiis-dsb | ✓ |
| Stage~1 Re-mapping and break-before-make | Break-before-make | MP.BBM1+dsb-tlbiis-dsb-dsb+dsb-isb | ⤫ |
| Stage~1 Re-mapping and break-before-make | Break-before-make | MP.BBM1+dsb-tlbiis-dsb-dsb+ctrl-isb | ⤫ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv+dsb+po | ✓ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv+dsbs | ✓ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv+dsb+dsb-isb | ⤫ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv+dsb+ctrl-isb | ⤫ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv+dmb+dsb-isb | ⤫ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv+dmb+po | ✓ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv.EL1+dsb-tlbiis-dsb+po | ⤫ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv.EL1+dsb-tlbiis-dsb+dmb | ⤫ |
| Translation-table-walk ordering | Inter-instruction ordering | MP.TTf.inv.EL1+dsb-tlbiis-dsb+dsb-isb | ⤫ |
| Translation-table-walk ordering | Multi-level translations | ROT.inv+dsb | ⤫ |
| Translation-table-walk ordering | Multi-level translations | ROT.inv+dmbst | ⤫ |
| Translation-table-walk ordering | Multi-level translations | LB+data-trfis | ⤫ |
| Translation-table-walk ordering | Multi-level translations | LB+addr-trfis | ⤫ |
| Translation-table-walk ordering | Multi-level translations | RWC.RTfR.inv+addr+dmb | ⤫ |
| Translation-table-walk ordering | Multi-level translations | RWC.RTR.EL1+dsb-isb+dsb-tlbi-dsb | ⤫ |
| Translation-table-walk ordering | Multi-level translations | SB.TfTf.inv+dsb-isbs | ⤫ |
| Translation-table-walk ordering | Multi-level translations | SB.TfTf.inv+dmb-ctrl-isbs | ⤫ |
| Translation-table-walk ordering | Multi-level translations | IRIW.TTf.TTf.inv+addrs | ⤫ |
| Translation-table-walk ordering | Multi-level translations | ISA2.RRTf.inv+dsb+addr+addr | ⤫ |
| Translation-table-walk ordering | Multi-level translations | ISA2.RRTf.inv+dsb+data+addr | ⤫ |
| Translation-table-walk ordering | Multi-level translations | MP.RT.inv+trfi-data+addr | ⤫ |
| Translation-table-walk ordering | Multi-level translations | CoWTf.inv+rfi-addr | ✓ |
| Translation-table-walk ordering | Multi-level translations | WRC.TfRT+po+dsb-isb | ✓ |
| Translation-table-walk ordering | Multi-level translations | WRC.TfRT+dsb-tlbiis-dsb+dsb-isb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | CoWTf.inv+po-ctrl-isb+po | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TRTf.inv+dsb+dsb-isb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TRTf.inv+addrs | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TRTf.inv+dsbs | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TRTf.inv+dmbs | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TRTf.inv+pos | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TTTf.inv+addrs | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TTTf.inv+data+addr | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.RRTf.inv+dsb+dsb-isb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.RRTf.inv+dsb+ctrl-isb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.RRTf.inv+dsbs | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.RRTf.inv+dmbs | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.RRTf.inv+pos | ✓ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.RRTf.inv+addrs | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TfRR+dsb-isb+dsb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TfRR+ctrl-isb+dsb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TfRR+dsbs | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TfRR+po+dsb | ⤫ |
| Multi-copy atomicity | MCA translation-table-walk | WRC.TfRR+pos | ✓ |
| Multi-address-space support with ASIDs | ASIDs | CoWinvTa1.1+dsb-tlbiasidis-dsb-eret | ⤫ |
| Multi-address-space support with ASIDs | ASIDs | CoWinvTa2.1+dsb-tlbiasidis-dsb-eret | ✓ |