MP.RTT.EL1+dsb-tlbiis-tlbiis-dsb+dsb-isb

Description

forbidHere, we invalidate two different VAs, and perform their TLBIs together in the same thread, effectively allowing concurrent execution of the two TLBIs on the same core.

Source

[download toml source]
Page table setup Code
physical pa1 pa2 pa3; x |-> pa1; x ?-> invalid; y |-> pa2; z |-> pa3; z ?-> invalid; identity 0x1000 with code;
Thread 0
{R0=extz(0b0, 64), R1=pte3(x, page_table_base), R2=extz(0b0, 64), R3=pte3(z, page_table_base), R4=extz(page(x), 64), R5=extz(page(z), 64), R6=extz(0x1, 64), R7=y, PSTATE.EL=0b01}
STR X0,[X1] STR X2,[X3] DSB SY TLBI VAE1IS,X4 TLBI VAE1IS,X5 DSB SY STR X6,[X7]
Thread 1
{R1=y, R3=x, R5=z, VBAR_EL1=extz(0x1000, 64), PSTATE.EL=0b00, PSTATE.SP=0b0}
LDR X0,[X1] DSB SY ISB LDR X4,[X3] MOV X2,X4 LDR X4,[X5]
thread1_el1_handler
MOV X4,#1 MRS X13,ELR_EL1 ADD X13,X13,#4 MSR ELR_EL1,X13 ERET
Final State
1:X0=1 & 1:X2=0 & 1:X4=0

Execution Diagrams

Results

ETS MP.RTT.EL1+dsb-tlbiis-tlbiis-dsb+dsb-isb forbidden (0 of 4) 305092ms
strong MP.RTT.EL1+dsb-tlbiis-tlbiis-dsb+dsb-isb forbidden (0 of 4) 520042ms

Command-line invocation

isla-axiomatic --arch=/path/to/rems-project/isla-snapshots/aarch64.ir --config=/path/to/rems-project/isla/configs/aarch64_mmu_on.toml --footprint-config=/path/to/rems-project/isla/configs/aarch64.toml --model=/path/to/rems-project/systems-isla-tests/models/aarch64_mmu_strong_ETS.cat --armv8-page-tables --check-sat-using "(then dt2bv qe simplify solve-eqs bv)" --remove-uninteresting safe --dot . -t /path/to/litmus-tests/litmus-tests-armv8a-system-vmsa/tests/pgtable/HAND/MP.RTT.EL1+dsb-tlbiis-tlbiis-dsb+dsb-isb.litmus.toml

To generate diagrams we use model aarch64_mmu_no_axioms.cat to get diagrams of forbidden executions. To generate LaTeX sources of each test, pass --latex=.