LB.TT.inv+pos

Description

This is a variant of load buffering where the first thread’s store writes the descriptor that the translate for the second thread’s load translate-reads from, and symmetrically. This kind of self-satisfying cycle would be very problematic, and this test is forbidden.

Source

[download toml source]
Page table setup Code
physical pa1; x |-> invalid; y |-> invalid; x ?-> pa1; y ?-> pa1; *pa1 = 1; identity 0x1000 with code; identity 0x2000 with code;
Thread 0
{R1=x, R2=mkdesc3(oa=pa1), R3=pte3(y, page_table_base), VBAR_EL1=extz(0x1000, 64), PSTATE.SP=0b0, PSTATE.EL=0b00}
LDR X0,[X1] STR X2,[X3]
Thread 1
{R1=y, R2=mkdesc3(oa=pa1), R3=pte3(x, page_table_base), VBAR_EL1=extz(0x2000, 64), PSTATE.SP=0b0, PSTATE.EL=0b00}
LDR X0,[X1] STR X2,[X3]
thread0_el1_handler
MOV X0,#0 MRS X13,ELR_EL1 ADD X13,X13,#4 MSR ELR_EL1,X13 ERET
thread1_el1_handler
MOV X0,#0 MRS X13,ELR_EL1 ADD X13,X13,#4 MSR ELR_EL1,X13 ERET
Final State
0:X0 = 1 & 1:X0=1

Execution Diagrams

Results

ETS LB.TT.inv+pos forbidden (0 of 4) 16545ms
strong LB.TT.inv+pos forbidden (0 of 4) 15481ms

Command-line invocation

isla-axiomatic --arch=/path/to/rems-project/isla-snapshots/aarch64.ir --config=/path/to/rems-project/isla/configs/aarch64_mmu_on.toml --footprint-config=/path/to/rems-project/isla/configs/aarch64.toml --model=/path/to/rems-project/systems-isla-tests/models/aarch64_mmu_strong_ETS.cat --armv8-page-tables --check-sat-using "(then dt2bv qe simplify solve-eqs bv)" --remove-uninteresting safe --dot . -t /path/to/litmus-tests/litmus-tests-armv8a-system-vmsa/tests/pgtable/HAND/LB.TT.inv+pos.litmus.toml

To generate diagrams we use model aarch64_mmu_no_axioms.cat to get diagrams of forbidden executions. To generate LaTeX sources of each test, pass --latex=.