CoWR.inv

Description

forbidWriting a new entry to the page-table then loading the location again performs a normal data memory read.We do not adapt all of the standard “user” data memory tests here with translation tables as memory locations. Instead, we just give one representative co-shaped example.

Source

[download toml source]
Page table setup Code
physical pa1; x |-> invalid; x ?-> pa1; y |-> pa1;
Thread 0
{R0=desc3(y, page_table_base), R1=pte3(x, page_table_base), R3=pte3(x, page_table_base), VBAR_EL1=extz(0x1000, 64), PSTATE.SP=0b0}
STR X0,[X1] LDR X2,[X3]
Final State
0:X2 = 0

Execution Diagrams

Results

ETS CoWR.inv forbidden (0 of 1) 1104ms
strong CoWR.inv forbidden (0 of 1) 825ms

Command-line invocation

isla-axiomatic --arch=/path/to/rems-project/isla-snapshots/aarch64.ir --config=/path/to/rems-project/isla/configs/aarch64_mmu_on.toml --footprint-config=/path/to/rems-project/isla/configs/aarch64.toml --model=/path/to/rems-project/systems-isla-tests/models/aarch64_mmu_strong_ETS.cat --armv8-page-tables --check-sat-using "(then dt2bv qe simplify solve-eqs bv)" --remove-uninteresting safe --dot . -t /path/to/litmus-tests/litmus-tests-armv8a-system-vmsa/tests/pgtable/HAND/CoWR.inv.litmus.toml

To generate diagrams we use model aarch64_mmu_no_axioms.cat to get diagrams of forbidden executions. To generate LaTeX sources of each test, pass --latex=.