CoRR0.alias+po

Description

This is the classic coherence shape. Here, we ask whether two reads with different VAs but which map to the same PA are allowed to re-order with respect to each other if they read from different writes. For Arm, they are not, as coherence is with respect to physical addresses.

Source

[download toml source]
Page table setup Code
physical pa1; x |-> pa1; y |-> pa1; *pa1 = 0;
Thread 0
{R0=extz(0b1, 64), R1=x}
STR X0,[X1]
Thread 1
{R1=x, R3=y, PSTATE.SP=0b0, PSTATE.EL=0b00}
LDR X0,[X1] LDR X2,[X3]
Final State
1:X0=1 & 1:X2=0

Execution Diagrams

Results

ETS CoRR0.alias+po forbidden (0 of 1) 1420ms
strong CoRR0.alias+po forbidden (0 of 1) 2512ms

Command-line invocation

isla-axiomatic --arch=/path/to/rems-project/isla-snapshots/aarch64.ir --config=/path/to/rems-project/isla/configs/aarch64_mmu_on.toml --footprint-config=/path/to/rems-project/isla/configs/aarch64.toml --model=/path/to/rems-project/systems-isla-tests/models/aarch64_mmu_strong_ETS.cat --armv8-page-tables --check-sat-using "(then dt2bv qe simplify solve-eqs bv)" --remove-uninteresting safe --dot . -t /path/to/litmus-tests/litmus-tests-armv8a-system-vmsa/tests/pgtable/HAND/CoRR0.alias+po.litmus.toml

To generate diagrams we use model aarch64_mmu_no_axioms.cat to get diagrams of forbidden executions. To generate LaTeX sources of each test, pass --latex=.