Advanced Computer Architecture Supervision 4
Recommended reading
Computer Architecture: A Quantitative Approach (5th edition) by Hennessy and Patterson:
- Chapter 5: Thread-Level Parallelism
- Appendix F: Interconnection Networks
(Previous editions are also fine but may have different chapter names/numbers.)
Exercises
- If chip multiprocessors (CMPs) offer so many advantages why weren’t they exploited much earlier?
- The MESI protocol extends the MSI protocol by adding the E state.
- When is a cache line in state E?
- What optimisation does the addition of this extra state permit?
- Why might we use a directory-based cache coherency protocol in preference to a snoopy protocol?
- 2018 Paper 8 Question 2
- What differences are there between on-chip and internet-style networks, and how do these influence their design decisions?
- How might we choose whether to use a ring network or a bus?
- 2012 Paper 7 Question 5, parts a) and b) only
- 2021 Paper 9 Question 4, part c) only
- How many different processor designs do you think will be manufactured in the future: more or less than today?
- Suggest three ways that we can improve performance while reducing power consumption.