Advanced Computer Architecture Supervision 1

Exercises

What benefits does a move to a new CMOS fabrication technology node (e.g. moving from a 14nm to 10nm process) typically bring us?

How was it possible to increase the performance of microprocessors so dramatically between 1985 and 2000? Why is it difficult to continue on the same path now?

If you were trying to implement a pipelined processor, why might a RISC instruction set be preferable to a CISC one?

Three enhancements are proposed to improve the performance of a computer system. Each offers the following speedup: SpeedupA = 30, SpeedupB = 20, SpeedupC = 15. Only one enhancement is usable at a time, but multiple can be used over the course of an application.
1. If enhancements A and B are each usable for 25% of the time, what fraction of the time must enhancement C be used to achieve an overall speedup of 10?
2. Assume, for some benchmark, the possible fraction of use is 15% for each enhancement A and B and 70% for enhancement C. We want to maximise performance. If only one enhancement can be implemented, which should it be? If two enhancements can be implemented, which should be chosen?

Lecture 3 provides an equation for pipeline throughput (Slide 40).
1. Using this equation determine which pipeline depth gives the highest throughput, given the parameters below. What is the throughput, CPI and operating frequency of your pipeline? Assume that your initially start with a processor where S=1 and T=10ns. Pipeline stalls, requiring the pipeline to be flushed, occur every 10 cycles. Pipelining registers incur an overhead of 250ps (C).
2. What speedup does the optimal pipeline depth provide over a 5-stage pipeline?

Why did the power dissipated by desktop microprocessors during the 1980/90s rise when supply voltage was dropping and transistors were shrinking in size?

How might we go beyond the limitations of scalar processing and execute more than one instruction per clock cycle? (There are many possible answers to this.)