Technical reports

Early performance results from the prototype Morello microarchitecture

Robert N. M. Watson, Jessica Clarke, Peter Sewell, Jonathan Woodruff, Simon W. Moore, Graeme Barnes, Richard Grisenthwaite, Kathryn Stacer, Silviu Baranga, Alexander Richardson

September 2023, 19 pages

This work was supported by Innovate UK project “Digital Security by Design (DSbD) Technology Platform Prototype”, 105694.

Approved for public release; distribution is unlimited. Sponsored by the Defense Advanced Research Projects Agency (DARPA) under contract HR0011-22-C-0110 (“ETC”). The views, opinions, and/or findings contained in this report are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the Department of Defense or the U.S. Government.

We gratefully acknowledge UK Research and Innovation (UKRI), who sponsored the creation of Morello, and also the significant investment by DARPA in supporting the creation of CHERI and its earlier prototypes.

We also acknowledge Arm Limited and Google, Inc.

Abstract

Arm’s Morello is a first-generation, CHERI-enabled prototype CPU based on Arm’s Neoverse N1, as found in the N1SDP evaluation board. CHERI is an architectural feature that promises to dramatically improve software security through fine-grained memory protection and scalable compartmentalization. Supported by UKRI, Morello is a research platform to evaluate CHERI at an industrial scale through composition with a rich, contemporary, high-performance microarchitecture and full software stack at a scale unobtainable via ISA emulators or hardware simulators. This report provides a first look at software performance on Morello working with both the baseline microarchitecture and modified designs on FPGA, exploring the performance of the SPECint benchmark suite using multiple code generation models. This technical report is a snapshot of a living document tracking ongoing performance investigation and experimentation.

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BibTeX record

@TechReport{UCAM-CL-TR-986,
  author =	 {Watson, Robert N. M. and Clarke, Jessica and Sewell, Peter
          	  and Woodruff, Jonathan and Moore, Simon W. and Barnes,
          	  Graeme and Grisenthwaite, Richard and Stacer, Kathryn and
          	  Baranga, Silviu and Richardson, Alexander},
  title = 	 {{Early performance results from the prototype Morello
         	   microarchitecture}},
  year = 	 2023,
  month = 	 sep,
  url = 	 {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-986.pdf},
  institution =  {University of Cambridge, Computer Laboratory},
  doi = 	 {10.48456/tr-986},
  number = 	 {UCAM-CL-TR-986}
}