Technical reports
Three notes on the interpretation of Verilog
Daryl Stewart, Myra VanInwegen
January 2000, 47 pages
DOI | https://doi.org/10.48456/tr-485 |
Abstract
In order to simplify the many constructs available in the Verilog Hardware Description Language two methods were used to normalise code before analysis, scalarisation and hierarchy flattening.
A method for scalarising Verilog expressions is described and the replacement of expressions with scalarised versions is considered. This then forms the basis of an implementation of Verilog expression evaluation and normalization.
The organisation of hierarchical designs is described and an algorithm for flattening designs is derived from this.
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@TechReport{UCAM-CL-TR-485, author = {Stewart, Daryl and VanInwegen, Myra}, title = {{Three notes on the interpretation of Verilog}}, year = 2000, month = jan, url = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-485.pdf}, institution = {University of Cambridge, Computer Laboratory}, doi = {10.48456/tr-485}, number = {UCAM-CL-TR-485} }