home search a-z help
University of Cambridge Computer Laboratory
Comparative Architectures
Computer Laboratory > Course material 2006-07 > Comparative Architectures

Comparative Architectures
2006-07

Principal lecturer: Dr David Greaves
Taken by: Part II

Syllabus
Past exam questions

Example Classes

The three classes will be at 2:00pm in FW26 on 26, 28, 2nd Feb/Mar 2007.

Topics Please note: Because time ran out in the last lecture, the material from the end of Section 7 that was only briefly covered (on weak memory ordering, memory barrier instructions and atomic instructions) is not examinable this year.

Lecture Notes

The lecture notes are in seven PDF files:

Section 1

  • * Instruction set architectures. ISA history and compatibility, illustrated with IBM 360 and notable 8, 16, 32, 64 microprocessors. Review of stack/accumulator/GPR instruction sets in terms of byte sex, load-store versus register-memory, addressing modes, sub and un-aligned memory support. [3++ lectures]

    COMPARCH-1.pdf     ADDITIONAL MATERIAL

    Section 2

  • * Comparing architectures. Moore's Law, System versus chip performance. Performance metrics MIPS, MHz, FLOPS, SPEC. Power. Price. Compatibility [1+ lecture]

    COMPARCH-2.pdf     ADDITIONAL MATERIAL

    Section 3

  • * Advanced pipelining. The CPU performance equation. Structural hazards: long latency instructions. Data hazards: result forwarding and delayed loads. Control hazards: branch prediction, trace caches and avoiding branches. Exceptions. [3 lectures]

    COMPARCH-3.pdf     ADDITIONAL MATERIAL

    Section 4

  • * Super-scalar techniques. Instruction Level Parallelism (ILP). Dynamic out-of-order execution: Tomasulo, embedded dataflow, virtual registers. [2 lectures]

    COMPARCH-4.pdf     ADDITIONAL MATERIAL

    Section 5

  • * Beyond super-scalar. The limits of ILP. Alternative architectures: VLIW processors and custom VLIW synthesis, Tri-media, SMT, SCMP [2 lectures]

    COMPARCH-5.pdf     ADDITIONAL MATERIAL

    Section 6

  • * Memory hierarchy. Cache configurations. Latency versus bandwidth. Re-ordering and coherence. Programming for caches. [2 lectures]

    COMPARCH-6.pdf     ADDITIONAL MATERIAL

    Section 7

  • * Multi-processor systems. Multi-core devices, multi-processor cache coherency. Interconnects for NUMA, message passing clusters and network on chip: OCP, ARM AXI. Models for weak memory ordering. [2 lectures]

    COMPARCH-7.pdf     ADDITIONAL MATERIAL

    The lecturing time allocated to each section is only nominal.

Sources Cited by Dr Greaves

The 'additional material' is currently not allocated to specific lectures but will become so.

All other materials: see the ALL subdirectory for now.

Sources Cited by Dr Pratt

Sources of extra information and interesting articles: