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Part II CST SoC D/M Slide Pack 7 (Tools/Tech/Eng)
SoC Engineering and Associated Tools
SoC Engineering and Associated Tools
Static Timing Analyser Tool
RAM Macrocell Compiler Tool
Test Program Generator Tool
Scan Path Insertion and JTAG standard test port.
Architectural Exploration and Design Partition
Architectural Exploration and Design Partition
H/W to S/W Interfacing Techniques
H/W Design Partition
Chip Types and Classifications
IC Taxonomy
Semi-custom (cell-based) Design
Gate Arrays and Field-Programmable Logic.
FPGA - Field Programmable Gate Array
PALs and CPLDs
H/W versus S/W Design Partition Principles
Legacy H/W S/W Design Partition
An old example example: The Cambridge Fast Ring two chip set.
Partitioning example: An external RS-232/POTS Modem.
Partitioning example: A Bluetooth Module.
Cell Library Tour
Silicon Power and Technology
Silicon Power and Technology
90 Nanometer Gate Length.
Delay Estimation Formula.
Power Estimation Formula
Power Consumption Example
Dynamic Clock Gating
Dynamic Power Gating
Dynamic Frequency Scaling
Dynamic Voltage Scaling