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ACS SoC D/M: Section 3.2: High-Level Logic Synthesis

High-Level Synthesis

  • High-Level Synthesis
  • Logic Synthesis and Time/Space Exchange
  • Higher level: Behavioural or Logical ?

    Behavioural Expression

  • Behavioural Expression
  • Beyond Pure RTL: Behavioural descriptions of hardware.
  • More-advanced behavioural specification:
  • Static and Dynamic Scheduling
  • Synopsys Behavioural Compiler
  • Shortcomings of Verilog and VHDL (for HL-Synthesis).
  • Motivations to do better.
  • Channel Communications
  • Synthesis from C and other programing languages.
  • Kiwi : Compiling Concurrent Programs to Hardware
  • State charts and Graphical `languages'
  • Behavioural Summary

    Synthesis from Logical Specifications

  • Synthesis from Logical Specifications
  • Automatic Synthesis of Transactors and Bus Monitors
  • Synthesis from Rules (SAT-based idea).
  • Rule-based hardware generation (BlueSpec)
  • Automatic Synthesis of Glue and Interface Automata
  • Synthesis from Formal Specification
  • Refinement from a specification to implementation.

    Back-end logic synthesis.

  • Back-end logic synthesis.
  • Synthesis goals: logic minimisation, delay area, power.
  • D-type migration.
  • Restructuring to accommodate timespecs.
  • Logic Minimisation.
  • Don't care states in HDL.
  • Instance optimisation problem and uniquify.