Back-end logic synthesis.

The back-end of the logic synthesis procedure involves optimisation. Such optimisation can consume massive amounts of CPU time, although typically a designer will not use more than a day's worth of CPU time on any particular job. Instead, she will partition the synthesis process into day-sized jobs, or her boss will structure the team that way. The back-end synthesis procedures include

• Restructuring procedures where the contents of flip-flops changes.
• Restructuring procedures where the contents of flip-flops is unchanged and only the combinatorial logic changes.
• Insertion of special logic patterns for testing.

Generally, one of the aims of such restructuring is to raise the system clock frequency, and hence its throughput. Sometimes, however, the aim is instead to reduce the power consumption. The process of ensuring a chip or system will run at its target clock frequency is known as obtaining 'timing closure'.