Automatic Synthesis of Transactors and Bus Monitors

In a previous slidepack we looked at Automatic Synthesis of Transactors and Bus Monitors...

Temporal logics, such as PSL and SVA can be compiled to automata that serve as:

• Checkers for Dynamic Validation (e.g.\ a bus protocol monitor),
• Transactors (for converting from TLM to net-level) in ESL.

Transactor Synthesis

A behavioural program that drives outputs can be 'reflected' to become a checker by interpreting the assignments as assertions.