Often the same subcircuit is used several times in a design on a single chip. The synthesiser can either be given the whole chip to do a global job on, or else it can be given the subcircuit once and the synthesiser output will be used in multiple instances.
There are various pros and cons: for instance, if multiple instances of the same module are used, hand optimisations and test procedures will work for each instance; but if the synthesiser is allowed to work on the whole design it may optimise across the previous instance boundaries resulting in a more compact result.
If, in some instances of a subcircuit, some inputs are tied off to fixed logic values, or an output is not used, then that instance will carry redundant logic. The benefit of synthesising it only once, meaning it will only have to be debugged and analysed for testability at the gate level once, may outweigh the cost of the wasted silicon. The command to the industry standard Synopsys compiler for making multiple instances separate, so that they are treated individually, is `uniqify'. <p><li>Apr 09: Exploiting System-Level Concurrency Abstractions for Hardware Descriptions, David J. Greaves, Satnam Singh. Technical Report MSR-TR-2009-48, Microsoft Corporation, Cambridge 2009. http://research.microsoft.com/apps/pubs/default.aspx?id=80442 Bluespec SystemVerilog: Efficient, Correct RTL from High-Level Specifications ------------------------------# The Challenges of Synthesizing Hardware from C-Like Languages http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01704728 Comparison of high level design methodologies for algorithmic IPs ... ------------------------------# http://www.impulseaccelerated.com/Videos/ ------------------------------# http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=01459818