Many RTL synthesisers allows and implied program counter (state machine).
reg [2:0] yout;
always
begin
@(posedge clk) yout = 1;
@(posedge clk) yout = 4;
@(posedge clk) yout = 3;
end
Some conditional branches may be possible, for instance, the second assignment could be changed to :
if (din) @(posedge clk) yout = 4;