I'm a post-doctoral researcher here at the University of Cambridge in the Computer Laboratory. I work in the Computer Architecture Group and in collaboration with other researchers throughout the world.

From 1 September 2008 I hold a Research Fellowship from the UK's Royal Academy of Engineering and EPSRC. This supports my research into compiler-directed power saving in multicore processors. As part of my Fellowship I spent 2010 at Harvard working with David Brooks and his research team. Now that I'm in Cambridge, my Fellowship allows me to work part-time at ARM.

I am also technical leader of the compilation cluster in the HiPEAC network of excellence and a college research associate at St John's.

Prior to joining Cambridge, I was part of the Compiler and Architecture Design Group at the University of Edinburgh's School of Informatics.

Research Associate in JIT Compilation for Overcoming Multicore Processor Errors

There is a vacancy for a Research Associate or PostDoc to work on a new grant looking at slowing down processor ageing and reacting to hard errors using a managed runtime environment or JIT. More details can be found here. Please contact me if you have questions about this position.

If you're a PhD student, please consider submitting to the first Doctoral Workshop at ASPLOS 2012, which I'm co-organising with Onur Mutlu. If you're faculty, please consider becoming a mentor for the students that are accepted to the workshop.

My research is looking at ways of using the compiler to adapt the hardware. My PhD thesis considered energy savings in superscalar processors and using the compiler to give hints to the processor about the resources needed for the next few instructions. The compiler, of course, has the advantage that it knows a bit about the future. I considered the issue queue and register file for optimisation. My current research areas include:

• Compilation for multicore processors: energy saving, performance and parallelisation.
• Using machine learning to explore microarchitecture and compiler design spaces considering the tradeoffs between performance and energy.
• Compiler-directed optimisations for energy reduction in the cache hierarchy, especially the instruction cache.
• Research into energy savings and complexity reduction within a processor pipeline.
• Compiler-directed schemes for increasing processor reliability and mitigating process variation.

I am interested in collaborations with other researchers on any of the above. If you would like to work with me then please send me an email.

• Program Committee Member for SCOPES 2012.
• Program Co-Chair of 1st ASPLOS Doctoral Workshop, 2012.
• Distinguished Reviewer for HiPEAC 2012.
• Program Committee Member for SCOPES 2011.
• Program Committee Member for SBAC-PAD 2010.
• Program Committee Member for SCOPES 2010.
• Program Committee Member for MEDEA Workshop 2009.
• Program Committee Member for SBAC-PAD 2009.
• Program Committee Member for MEDEA Workshop 2008.
• Program Committee Member for MEDEA Workshop 2007.